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| DATA SHEET PD753036, 753036(A) 4-BIT SINGLE-CHIP MICROCONTROLLER MOS INTEGRATED CIRCUIT DESCRIPTION The PD753036 is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. It has an on-chip LCD controller/driver with a larger ROM capacity and extended CPU functions compared with the conventional PD75336, and can provide high-speed operation at a low supply voltage of 1.8 V. It can be supplied in a small plastic TQFP package (12 x 12 mm) and is suitable for small sets using LCD panels. A stricter quality assurance program applies the PD753036(A) compared to the PD753036 (standard model). (In terms of NEC's quality grading, this is a "special" grade product.) For details of functions refer to the following User's Manual. PD753036 User's Manual: U10201E FEATURES * Low voltage operation VDD = 1.8 to 5.5 V * Can be driven by two 1.5 V batteries * Internal programmable LCD controller/driver * Internal A/D converter which can be operated at a low voltage * 8-bit resolution x 8 channels (successive approximation type) * On-chip memory * Program memory (ROM): 16384 x 8 bits * Data memory (RAM): 768 x 4 bits * Capable of high-speed operation and variable instruction execution time for power saving * 0.95, 1.91, 3.81, 15.3 s (@ 4.19 MHz) * 0.67, 1.33, 2.67, 10.7 s (@ 6.0 MHz) * 122 s (@ 32.768 kHz) * Small plastic TQFP (12 x 12 mm) * Suitable for small sets such as cameras * One-time PROM: PD75P3036 APPLICATION Radio transmitter/receiver, compact disc player, rice cooker, home bakery, etc. ORDERING INFORMATION Part number Package 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5 mm pitch) 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) Quality grade Standard Standard Special PD753036GC-xxx-3B9 PD753036GK-xxx-BE9 PD753036GC(A)-xxx-3B9 Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Unless otherwise specified, the PD753036 is treated as the representative model throughout this document. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U11353EJ4V0DS00 (4th edition) Date Published June 2000 N CP(K) Printed in Japan The mark shows major revised points. (c) 1996, 2000 PD753036, 753036(A) Functional Outline Parameter Minimum instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (main system clock: @4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: @6.0 MHz operation) * 122 s (subsystem clock: @32.768 kHz operation) ROM RAM General purpose register 16384 x 8 bits 768 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 8 20 8 8 Also used for segment pins On-chip pull-up resistors can be specified by using mask option 13 V withstand voltage On-chip pull-up resistors can be specified by using software: 27 On-chip memory Input/ output port CMOS input CMOS input/output Bit port output N-ch open-drain input/output pins Total 44 * Segment selection: * Display mode selection: 12/16/20 segments (can be changed to bit port output in unit of 4; max. 8) Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) LCD controller/driver On-chip split resistor for LCD drive can be specified by using mask option Timer 5 channels * 8-bit timer/event counter: 3 channels (16-bit timer/event counter, career generator, timer with gate) * Basic interval/watchdog timer: 1 channel * Watch timer: 1 channel * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit * 2-wire serial I/O mode * SBI mode 8-bit resolution x 8 channels (1.8 V AVREF VDD) 16 bits * , 524, 262, 65.5 kHz (main system clock: @4.19 MHz operation) * , 750, 375, 93.8 kHz (main system clock: @6.0 MHz operation) * 2, 4, 32 kHz (main system clock: @4.19 MHz operation or subsystem clock: @32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (main system clock: @6.0 MHz operation) External: 3, Internal: 5 External: 1, Internal: 1 * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode VDD = 1.8 to 5.5 V * 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5 mm pitch) Serial interface A/D converter Bit sequential buffer (BSB) Clock output (PCL) Buzzer output (BUZ) Vectored interrupts Test input System clock oscillator Standby function Power supply voltage Package 2 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 5 2. BLOCK DIAGRAM ............................................................................................................................... 7 3. PIN 3.1 3.2 3.3 3.4 FUNCTION ...................................................................................................................................... 8 Port Pins ...................................................................................................................................... 8 Non-Port Pins ...........................................................................................................................10 Pin Input/Output Circuits ........................................................................................................12 Recommended Connections for Unused Pins .....................................................................15 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ............................................. 16 4.1 Difference between Mk I and Mk II ..........................................................................................16 4.2 Setting Method of Stack Bank Select Register (SBS).......................................................... 17 5. MEMORY CONFIGURATION ............................................................................................................18 6. PERIPHERAL HARDWARE FUNCTIONS .......................................................................................21 6.1 Digital I/O Port ..........................................................................................................................21 6.2 Clock Generator .......................................................................................................................22 6.3 Subsystem Clock Oscillator Control Functions ..................................................................23 6.4 Clock Output Circuit ................................................................................................................24 6.5 Basic Interval Timer/Watchdog Timer ...................................................................................25 6.6 Watch Timer ..............................................................................................................................26 6.7 Timer/Event Counter ................................................................................................................27 6.8 Serial Interface .........................................................................................................................31 6.9 LCD Controller/Driver ..............................................................................................................33 6.10 A/D Converter ..........................................................................................................................35 6.11 Bit Sequential Buffer ..............................................................................................................36 7. INTERRUPT FUNCTION AND TEST FUNCTION ............................................................................ 37 8. STANDBY FUNCTION .......................................................................................................................39 9. RESET FUNCTION ............................................................................................................................40 10. MASK OPTION ...................................................................................................................................43 11. INSTRUCTION SETS .........................................................................................................................44 12. ELECTRICAL CHARACTERISTICS .................................................................................................54 13. CHARACTERISTIC CURVE (reference) ..........................................................................................69 14. PACKAGE DRAWINGS .....................................................................................................................73 Data Sheet U11353EJ4V0DS00 3 PD753036, 753036(A) 15. RECOMMENDED SOLDERING CONDITIONS ................................................................................75 APPENDIX A. PD75336, 753036, 75P3036 FUNCTION LIST ...........................................................76 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................78 APPENDIX C. RELATED DOCUMENTS ...............................................................................................82 4 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 1. PIN CONFIGURATION (TOP VIEW) * 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) PD753036GC-xxx-3B9, 753036GC(A)-xxx-3B9 * 80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5 mm pitch) PD753036GK-xxx-BE9 P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 RESET X2 X1 Note IC XT2 S31/BP7 S30/BP6 S29/BP5 S28/BP4 S27/BP3 S26/BP2 S25/BP1 S24/BP0 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 XT1 VDD AVREF AVSS AN5 AN4 AN3 AN2 AN1 AN0 P83/AN7 P82/AN6 P81/TI2 P80/TI1 P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1 Note Connect the IC (Internally Connected) pin directly to VDD. P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P40 P41 P42 P43 VSS COM0 Data Sheet U11353EJ4V0DS00 5 PD753036, 753036(A) P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 BP0-BP7 KR0-KR7 SCK SI SO SB0, SB1 RESET S12-S31 COM0-COM3 : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 8 : Bit Port 0-7 : Key Return 0-7 : Serial Clock : Serial Input : Serial Output : Serial Data Bus 0, 1 : Reset : Segment Output 12-31 : Common Output 0-3 VLC0-VLC2 BIAS LCDCL SYNC TI0-TI2 PTO0-PTO2 BUZ PCL AVREF AVSS AN0-AN7 INT2 X1, X2 XT1, XT2 VDD VSS IC : LCD Power Supply 0-2 : LCD Power Supply Bias Control : LCD Clock : LCD Synchronization : Timer Input 0-2 : Programmable Timer Output 0-2 : Buzzer Clock : Programmable Clock : Analog Reference : Analog Ground : Analog Input 0-7 : External Test Input 2 : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 : Positive Power Supply : Ground : Internally Connected INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4 6 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 2. BLOCK DIAGRAM TI0/P13 PTO0/P20 AN0-AN5 AN6/P82 AN7/P83 8 AVREF AVSS 8-bit timer/event counter #0 INTT0 TOUT0 A/D converter Basic interval timer/ watchdog timer Port0 Port1 Program counter (14) ALU SP (8) CY SBS Bank Port2 Port3 Port4 Port5 General reg. Program memory (ROM) 16384 x 8 bits Decode and control Port6 Port7 Data memory (RAM) 768 x 4 bits Port8 4 4 4 4 4 4 4 4 4 P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 INTBT INTT1 TI1/P80 PTO1/P21 TI2/P81 PTO2/PCL/P22 BUZ/P23 SI/SB1/P03 S0/SB0/P02 SCK/P01 INT0/P10 INT1/P11 INT4/P00 INT2/P12 KR0/P60KR7/P73 8-bit timer/event counter #1 8-bit timer/event counter #2 Cascaded 16-bit timer/ event timer INTT2 Watch timer INTW fLCD Clocked serial interface INTCSI TOUT0 12 S12-S23 LCD controller/ driver fx/2N Clock output control PCL/P22 Clock divider Sub CPU clock System clock generator 8 4 Interrupt control fLCD 8 Bit seq. buffer (16) Stand by Main control S24/BP0S31/BP7 COM0-COM3 VLC0 VLC1 VLC2 BIAS LCDCL/P30 SYNC/P31 IC VDD VSS RESET XT1XT2 X1 X2 Data Sheet U11353EJ4V0DS00 7 PD753036, 753036(A) 3. PIN FUNCTION 3.1 Port Pins (1/2) Alternate Function INT4 SCK SO/SB0 SI/SB1 Input INT0 INT1 INT2 TI0 Input/Output PTO0 PTO1 PCL/PTO2 BUZ Input/Output LCDCL SYNC - - - Programmable 4-bit input/output port (PORT3). This port can be specified input/output in bit units. Connections of on-chip pull-up resistor can be specified by software in 4-bit units. N-ch open-drain 4-bit input/output port Yes (PORT4). A pull-up resistor can be contained bit-wise (mask option). In the open-drain mode, withstands up to 13 V. N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). In the open-drain mode, withstands up to 13 V. High level (when pullup resistors are contained) or high impedance High level (when pullup resistors are provided) or high impedance M-D No Input E-B 4-bit input port (PORT1) Connections of on-chip pull-up resistors can be specified by software in 4-bit units. P10/INT0 can select noise eliminating circuit. 4-bit input/output port (PORT2) Connections of on-chip pull-up resistors can be specified by software in 4-bit units. No Input 8-bit Access No State after Reset Input I/O Circuit Type Note 1 B F -A F -B M -C B -C Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 Input/Output Input Function 4-bit input port (PORT0). For P01 to P03, connections of on-chip pull-up resistors can be specified by software in 3-bit units. No Input E-B P40-P43 Note 2 Input/Output P50-P53 Note 2 Input/Output - M-D Notes 1. 2. Circled characters indicate the Schmitt-trigger input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. 8 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 3.1 Port Pins (2/2) Alternate Function KR0 KR1 KR2 KR3 Input/Output KR4 KR5 KR6 KR7 Input/Output TI1 TI2 AN6 AN7 Output S24 S25 S26 S27 Output S28 S29 S30 S31 1-bit output port (BIT PORT) Also used for segment output pins. No Note 2 H-A 4-bit input/output port (PORT8). Connections of on-chip pull-up resistors can be specified by software in 4-bit units. No Input E -E 8-bit Access Yes State after Reset Input I/O Circuit Type Note 1 F -A Pin Name P60 P61 P62 P63 P70 P71 P72 P73 P80 P81 P82 P83 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 Input/Output Input/Output Function Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bit-wise. Connections of on-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input/output port (PORT7). Connections of on-chip pull-up resistors can be specified by software in 4-bit units. Input F -A Y-B Notes 1. 2. Circled characters indicate the Schmitt-trigger input. BP0 through BP7 select VLC1 as an input source. However, the output levels change depending on the external circuit of BP0 through BP7 and VLC1. Example Because BP0 through BP7 are mutually connected inside the PD753036, the output levels of BP0 through BP7 are determined by R1, R2, and R3. PD753036 VDD R2 BP0 ON VLC1 R1 ON BP1 R3 Data Sheet U11353EJ4V0DS00 9 PD753036, 753036(A) 3.2 Non-Port Pins (1/2) Alternate Function P13 P80 P81 Output P20 P21 P22 Clock output P23 Optional frequency output (for buzzer output or system clock trimming) Serial clock input/output Serial data output Serial data bus input/output Serial data input Serial data bus input/output Edge detection vectored interrupt input (both rising edge and falling edge detection) Edge detection vectored interrupt input (detection edge can be selected) INT0/P10 can select noise eliminator. Pin Name TI0 TI1 TI2 PTO0 PTO1 PTO2 PCL BUZ Input/Output Input Function Inputs external event pulses to the timer/event counter. State after Reset Input I/O Circuit Type Note 1 B -C E -E Timer/event counter output Input E-B SCK SO/SB0 Input/Output P01 P02 Input F -A F -B SI/SB1 P03 M -C INT4 Input P00 Input B INT0 Input P10 Noise eliminator/ asynch selectable Asynchronous Asynchronous Input B -C INT1 INT2 AN0-AN5 AN6 AN7 AVREF AVSS KR0-KR3 KR4-KR7 S12-S23 S24-S31 COM0-COM3 VLC0-VLC2 - - Input Input Output Output Output - Input Input P11 P12 - P82 P83 - - P60-P63 P70-P73 - BP0-BP7 - - Edge-detection-testable input Input Input B -C Y Y-B Analog signal input for A/D converter A/D converter reference voltage input A/D converter reference GND Falling edge detection testable input Falling edge detection testable input Segment signal output Segment signal output Common signal output LCD drive power On-chip split resistor is enable (mask option). Output for external split resistor disconnect - - Input Input Note 2 Note 2 Note 2 - Z-N Z-N F -A F -A G-A H-A G-B - BIAS Output - Note 3 - Notes 1. 2. 3. Circled characters indicate the Schmitt trigger input. Each display output selects the following VLCX as input source. S12-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0. When a split resistor is contained ....... Low level When no split resistor is contained ...... High-impedance 10 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 3.2 Non-Port Pins (2/2) Alternate Function P30 P31 - State after Reset Input Input - I/O Circuit Type Note 1 E-B E-B - Pin Name LCDCL Note 2 SYNC Note 2 X1 X2 Input/Output Output Output Input - Function Clock output for externally expanded driver Clock output for externally expanded driver sync Crystal/ceramic connection pin for the main system clock oscillator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. Crystal connection pin for the subsystem clock oscillator. When the external clock is used, input the external clock to pin XT1 and the reverse phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin. System reset input (low level active) Internally connected. Connect directly to VDD. Positive power supply GND XT1 XT2 Input - - - - RESET IC VDD VSS Input - - - - - - - - - - - B - - - Notes 1. Circled characters indicate the Schmitt-trigger input. 2. These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. Data Sheet U11353EJ4V0DS00 11 PD753036, 753036(A) 3.3 Pin Input/Output Circuits The PD753036 pin input/output circuits are shown schematically. (1/3) TYPE A TYPE D VDD VDD Data P-ch IN N-ch Output disable N-ch P-ch OUT CMOS specification input buffer. TYPE B Push-pull output that can be placed in output high impedance (both P-ch, N-ch off). TYPE E-B VDD P.U.R. P.U.R. enable Data Type D Output disable P-ch IN IN/OUT Schmitt trigger input having hysteresis characteristic. Type A P.U.R. : Pull-Up Resistor TYPE B-C TYPE E-E VDO VDD P.U.R. P.U.R. enable P.U.R. enable Data Output disable IN Type D P.U.R P-ch P-ch IN/OUT Type A Type B P.U.R. : Pull-Up Resistor 12 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) (2/3) TYPE F-A VDD P.U.R. P.U.R. enable Data Output disable Type D P-ch IN/OUT OUT COM data Type B TYPE G-B VLC0 VLC1 P-ch N-ch P-ch N-ch P-ch N-ch VLC2 N-ch P-ch N-ch N-ch P-ch P.U.R. : Pull-Up Resistor TYPE F-B VDD P.U.R. P.U.R. enable VDD P-ch P-ch TYPE H-A Output disable (P) Data Output disable Output disable (N) SEG data IN/OUT Bit port data Output disable Type G-A OUT N-ch Type D P.U.R. : Pull-Up Resistor TYPE G-A TYPE M-C VDD VLC0 P-ch N-ch P.U.R. P.U.R. enable P-ch IN/OUT P-ch N-ch SEG data VLC2 P-ch N-ch N-ch P.U.R. : Pull-Up Resistor OUT N-ch Data Output disable N-ch VLC1 Data Sheet U11353EJ4V0DS00 13 PD753036, 753036(A) (3/3) TYPE M-D P.U.R. (Mask Option) IN/OUT Data Output disable Input instruction VDD P-ch P.U.R.Note Type A VDD TYPE Y-B VDD N-ch (+13 V withstand voltage) P.U.R. enable Data Type D Output disable P-ch IN/OUT Voltage limitation circuit (+13 V withstand voltage) Note This pull-up resistor operates only when an input instruction is executed without a pull-up resistor connected using the mask option (current flows from VDD to the pin when the pin is low). TYPE Y Port inputNote 2 Type Y P.U.R. : Pull-Up Resistor TYPE Z-N AVREF VDD P-ch IN VDD N-ch Sampling C AVSS Input enable + - Reference voltage AVSS Reference voltage (From voltage tap of series resistor string) ADEN N-ch AVSS 14 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 3.4 Recommended Connections for Unused Pins Table 3-1. List of Recommended Connections for Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL/PTO2 P23/BUZ P30/LCDCL P31/SYNC P32 P33 P40-P43 P50-P53 Input: Connect to VSS. Output: Connect to VSS. (Do not connect a pull-up resistor using the mask option.) P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80/TI1, P81/TI2 P82/AN6, P83/AN7 S12-S23 S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 BIAS Connect to VSS Only if all of VLC0-VLC2 are unused, connect to VSS. In other cases, no connection required. Connect to VSS Leave unconnected Connect to VSS or VDD Connect to VSS Leave unconnected Input: Individually connect to VSS or VDD via resistor Output: Leave unconnected Input: Individually connect to VSS or VDD via resistor Output: Leave unconnected Connect to VSS Connect to VSS or VDD Recommended Connection Connect to VSS or VDD Connect to VSS or VDD individually via resistor XT1 Note XT2 Note AN0-AN5 AVREF AVSS IC Connect to VDD directly Note When the subsystem clock is not used, set SOS. 0 to 1 (so as not to use the internal feedback resistor). Data Sheet U11353EJ4V0DS00 15 PD753036, 753036(A) 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I and Mk II The CPU of PD753036 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the Stack Bank Select register (SBS). * Mk I mode: * Mk II mode: Upward compatible with PD75336. Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. Incompatible with PD75336. Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I Mode Program memory (bytes) Number of stack bytes for subroutine instructions BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction 3-machine cycles 2-machine cycles 4-machine cycles 3-machine cycles 16384 2 bytes 3 bytes Mk II Mode Not available Available Caution Mk II supports a program area exceeding 16K bytes in the 75X and 75XL series. Therefore, this mode is useful for enhancing software compatibility with products exceeding 16K bytes. When Mk II mode is selected, the number of stack bytes used can be increased by 1 byte per stack compared with Mk I mode. When the CALL !addr instruction and CALLF !faddr instruction are used, the number of machine cycles becomes greater by 1. Therefore, use Mk I mode if the RAM efficiency and processing capability is more important than software compatibility. 16 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 10xxB Note at the beginning of a program. When using the Mk II mode, it must be initialized to 00xxB Note. Note The desired numbers must be set in the xx positions. Figure 4-1. Stack Bank Select Register Format Address F84H 3 SBS3 2 1 0 SBS0 Symbol SBS SBS2 SBS1 Stack area specification 0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Memory bank 2 Prohibited 0 Be sure to set bit 2 to 0. Mode switching specification 0 1 Mk II mode Mk I mode Caution Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode. Data Sheet U11353EJ4V0DS00 17 PD753036, 753036(A) 5. MEMORY CONFIGURATION * Program memory (ROM) ****** 16384 x 8 bits * Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an arbitrary address. * Addresses 0002H-000DH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt execution can start at an arbitrary address. * Addresses 0020H-007FH Table area referenced by the GETI instruction Note. Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. * Data memory (RAM) * Data area *** 768 words x 4 bits (000H-2FFH) * Peripheral hardware area *** 128 words x 4 bits (F80H-FFFH) 18 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Figure 5-1. Program Memory Map 7 0000H MBE 6 RBE 5 0 Internal reset start address (high-order 6 bits) " 0002H MBE RBE INTBT/INT4 start address (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) CALL !addr instruction subroutine entry address CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction " 0004H MBE RBE INT0 start address " 0006H MBE RBE INT1 start address " 0008H MBE RBE INTCSI start address BRCB !caddr instruction branch address " 000AH MBE RBE INTT0 start address " 000CH MBE RBE INTT1,INTT2 start address (high-order 6 bits) " (Iow-order 8 bits) BR $addr instruction relative branch address (-15 to -1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH Branch destination address and subroutine entry address when GETI instruction is executed BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address Note Can be performed only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of PC by executing the BR PCDE, BR PCXA instruction. Data Sheet U11353EJ4V0DS00 19 PD753036, 753036(A) Figure 5-2. Data Memory Map Data memory 000H General purpose register area 01FH 020H 0 256 x 4 (224 x 4) 0FFH 100H 256 x 4 (236 x 4) 1EBH 1ECH Display data memory Stack areaNote Data area static RAM (768 x 4) 256 x 4 2 1FFH 200H (20 x 4) 1 (32 x 4) Memory bank 2FFH Not incorporated F80H Peripheral hardware area 128 x 4 15 FFFH Note For stack area, one memory bank can be selected among memory bank 0-2. 20 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital I/O Port The following four types of I/O ports are available: * CMOS input (PORT0 and 1) : 8 pins 8 pins 8 pins * CMOS I/O (PORT2, 3, 6, 7, and 8) : 20 pins * N-ch open-drain I/O (PORT4 and 5) : * Bit port output (BP0 through BP7) Total : : 44 pins Table 6-1. Types and Features of Digital Ports Port Name PORT0 Function 4-bit input Operation & Features When using serial interface function, the dual function pin can function as the output port depending on the operation mode. 4-bit input port Remarks Also used as the INT4, SCK, SO/SB0, SI/SB1 pins. PORT1 Also used as the INT0INT2 and TI0 pins. Also used as the PTO0PTO2, PCL, BUZ pins. Also used as the LCDCL, SYNC pins. On-chip pull-up resistor can be specified bit-wise by mask option. PORT2 4-bit I/O Can be set to input mode or output mode in 4-bit units. Can be set to input mode or output mode in 1-bit units. PORT3 PORT4 PORT5 4-bit I/O (N-channel open-drain, 13 V withstand voltage) 4-bit I/O Can be set to input mode or output mode in 4-bit units. Ports 4 and 5 are paired and data can be input/ output in 8-bit units. PORT6 Can be set to input mode or output mode in 1-bit units. Can be set to input mode or output mode in 4-bit units. Ports 6 and 7 are paired and data can be input/ output in 8-bit units. Also used as the KR0-KR3 pins. PORT7 Also used as the KR4-KR7 pins. PORT8 Can be set to input mode or output mode in 4-bit units 1-bit output Outputs data bit-wise. Can be switched to LCD drive segment output S24-S31 by software. Also used as the TI1, TI2, AN6, AN7 pins. -- BP0-BP7 Data Sheet U11353EJ4V0DS00 21 PD753036, 753036(A) 6.2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is shown in Figure 6-1. The operation of the clock generation circuit is determined by the processor clock control register (PCC) and system clock control register (SCC). Two types of system clocks are available: main system clock and subsystem clock. Furthermore, the instruction execution time can be changed. * 0.95, 1.91, 3.81, 15.3 s (main system clock: at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: at 6.0 MHz operation) * 122 s (subsystem clock: at 32.768 kHz operation) Figure 6-1. Clock Generator Block Diagram * Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * LCD controller/driver * A/D converter * INT0 noise eliminator * Clock output circuit 1/1~1/4096 Divider 1/2 1/4 1/16 XT1 VDD XT2 X1 VDD X2 Main system clock oscillator fX Subsystems clock oscillator fXT LCD controller/driver Watch timer Selector WM.3 SCC SCC3 Internal bus SCC0 PCC PCC0 PCC1 4 PCC2 HALTNote STOPNote PCC3 R Q HALT F/F S Oscillation stop Selector Divider 1/4 * CPU * INT0 noise eliminator * Clock output circuit PCC2, PCC3 Clear STOP F/F Q S Wait release signal from BT RESET signal R Standby release signal from interrupt control circuit Note Instruction execution 22 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Remarks 1. 2. 3. 4. 5. 6. fX = Main system clock frequency fXT = Subsystem clock frequency = CPU clock PCC: Processor Clock Control Register SCC: System Clock Control Register One Clock cycle (tCY) of the CPU clock equal to one machine cycle of the instruction. 6.3 Subsystem Clock Oscillator Control Functions The PD753036 subsystem clock oscillator has the following two control functions. * Selects by software whether an on-chip feedback resistor is to be used or notNote. * Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (VDD 2.7 V). Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor), connect the XT1 pin to VSS, and open the XT2 pin to lower the supply current that is consumed in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (Refer to Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator SOS.0 Feedback resistor Inverter SOS.1 XT1 XT2 VDD Data Sheet U11353EJ4V0DS00 23 PD753036, 753036(A) 6.4 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the P22/PCL/PTO2 pin, and used to apply to the remote control waveform outputs and to supply clock pulses to the peripheral LSIs. * Clock output (PCL): , 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) , 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) Figure 6-3. Clock Output Circuit Block Diagram From clock generator fX/23 Selector fX/24 fX/26 Selector PCL/P22PTO2 From timer/event counter (channel 2) Output buffer PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 24 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 6.5 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. * * * * Interval timer operation to generate a reference time interrupt Watchdog timer operation to detect a runaway of program and reset the CPU Selects and counts the wait time when the standby mode is released Reads the contents of counting Figure 6-4 Basic Interval Timer/Watchdog Timer Block Diagram From clock generator fX/25 fX/27 MPX fX/29 fX/212 3 BT Clear Clear Basic interval timer (8-bit frequency divider) Set BT interrupt request flag Vectored interrupt IRQBT request signal Wait release signal when standby is released. Internal reset signal WDTM SET1Note 1 BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 8 Internal bus Note Instruction execution Data Sheet U11353EJ4V0DS00 25 PD753036, 753036(A) 6.6 Watch Timer The PD753036 has one channel of watch timer. The functions of the watch timer are as follows: * Sets the test flag (IRQM) with 0.5 sec interval. The standby mode can be released by the IRQM. * 0.5 sec interval can be created by both the main system clock (4.19 MHz) and subsystem clock (32.768 kHz). * Convenient for program debugging and checking as interval becomes 128 times shorter (3.91 ms) with the fast feed mode. * Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the BUZ pin (P23), usable for buzzer and trimming of system clock frequencies. * Clears the frequency divider to make the clock start with zero seconds. Figure 6-5. Watch Timer Block Diagram fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 From clock generator (32.768 kHz) fXT (32.768 kHz) Selector fLCD fW (32.768 kHz) 4 kHz 2 kHz fW fW 23 24 Divider fW 214 2 Hz 0.5 sec Selector INTW IRQW set signal Clear Selector Output buffer P23/BUZ WM WM7 0 WM5 WM4 WM3 WM2 WM1 WM0 PORT2.3 P23 output latch PMGB bit 2 Port 2 input/ output mode 8 Bit test instruction Internal bus The values enclosed in parentheses are applied when fX = 4.19 MHz and fXT = 32.768 kHz. 26 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 6.7 Timer/Event Counter The PD753036 has three channels of timer/event counters. The configuration is shown in Figures 6-6 through 6-8. The functions of the timer/event counter are as follows: * * * * Programmable interval timer operation Square wave output of any frequency to the PTOn pin. (n = 0-2) Event counter operation Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency division operation). * Supplies the serial shift clock to the serial interface circuit. * Reads the counting value. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Mode 8-bit timer/event counter mode Gate control function PWM pulse generator mode 16-bit timer/event counter mode Gate control function Carrier generator mode Yes NoNote No No NoNote No Yes No No Yes Yes Yes Yes Yes Yes Channel 1 Channel 2 Note Used for gate control signal generation Data Sheet U11353EJ4V0DS00 27 28 8 - PORT1.3 Input buffer TI0/P13 From clock generator fx/24 fx/26 fx/28 fx/210 MPX Data Sheet U11353EJ4V0DS00 Figure 6-6. Timer/Event Counter Block Diagram (channel 0) Internal bus SET1Note TM0 TM06 TM05 TM04 TM03 TM02 0 0 8 8 TMOD0 Modulo register (8) TOE0 T0 enable flag PORT2.0 PGMB bit 2 Port 2 P20 input/output output latch mode To serial interface 8 TOUT0 Match Comparator (8) 8 Reset T0 Count register (8) CP Clear INTT0 IRQT0 set signal TOUT F/F Output buffer P20/PTO0 Timer operation start RESET IRQT0 clear signal To timer/event counter (channel 2) PD753036, 753036(A) Note Instruction execution Caution When setting TM0, be sure to set bits 0 and 1 to 0. Figure 6-7. Timer/Event Counter Block Diagram (channel 1) Internal bus 8 - SET1 Note TM1 TM16 TM15 TM14 TM13 TM12 TM11 TM10 Decoder 8 TMOD1 PORT1.2 Modulo register (8) 8 Input buffer TI1/P80 Data Sheet U11353EJ4V0DS00 Timer/event counter output (channel 2) TOE1 T1 enable flag PORT2.1 P21 output latch PMGB.2 Port 2 input/output mode Comparator (8) 8 MPX CP Count register (8) Clear T1 Match TOUT F/F Reset P21/PTO1 Output buffer From clock generator fx/2 fx/26 fx/28 fx/210 fx/212 5 RESET Timer operation start 16 bit timer/event counter mode Selector IRQT1 set signal PD753036, 753036(A) Timer/event counter match signal (channel 2) (When 16-bit timer/event counter mode) Timer/event counter reload signal (channel 2) INTT1 IRQT1 set signal Timer/event counter comparator (channel 2) (When 16-bit timer/event counter mode) Note Instruction execution 29 Selector Selector TI2/P81 fx fx/2 From clock fx/24 generator fx/26 fx/28 fx/210 Data Sheet U11353EJ4V0DS00 MPX CP T2 Count register (8) Clear 8 Reset Overflow Carrier generator mode Selector 30 8 SET1 Note Figure 6-8. Timer/Event Counter Block Diagram (channel 2) Internal bus 8 TM2 TM26 TM25 TM24 TM23 TM22 TM21 TM20 8 TMOD2H TMOD2 TGCE 8 TC2 TOE2REMC NRZB NRZ Reload Modulo register for high level period setup PORT1.2 Decoder 8 Modulo register (8) 8 PORT2.2 PMGB.2 P22 Port 2 output latch input/output MPX (8) 8 Comparator (8) P22/PCL/PTO2 Match Input buffer TOUT F/F Output buffer Timer/event counter clock input (channel 1) 16-bit timer/event counter mode INTT2 IRQT2 set signal IRQT2 clear signal Timer operation start RESET Timer event counter TOUT F/F (channel 0) Timer/event counter clear signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When carrier generator mode) From clock generator PD753036, 753036(A) Note Instruction execution PD753036, 753036(A) 6.8 Serial Interface The PD753036 incorporates a clock-synchronous 8-bit serial interface and can be used in the following four modes. * * * * Operation stop mode 3-wire serial I/O mode 2-wire serial I/O mode SBI mode Data Sheet U11353EJ4V0DS00 31 ACKE P02/SO/SB0 Selector Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD Busy/ acknowledge output circuit BSYE ACKT 32 8/4 Bit test CSIM P03/SI/SB1 Selector Data Sheet U11353EJ4V0DS00 Figure 6-9. Serial Interface Block Diagram Internal bus 8 8 8 Bit manipulation SBIC RELT CMDT (8) SET CLR Shift register (SIO) (8) D Q SO latch Bit test Slave address register (SVA) (8) Match signal Address comparator P01/SCK Serial clock counter INTCSI INTCSI control circuit IRQCSI set signal PD753036, 753036(A) P01 output Iatch Serial clock control circuit Serial clock selector fX/23 fX/24 fX/26 TOUT0 (from timer/event counter (channel 0)) External SCK PD753036, 753036(A) 6.9 LCD Controller/Driver The PD753036 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the panel directly. The PD753036 LCD controller/driver functions are as follows: * Display data memory is read automatically by DMA operation and segment and common signals are generated. * Display mode can be selected from among the following five: (1) Static (2) 1/2 duty (time multiplexing by 2), 1/2 bias (3) 1/3 duty (time multiplexing by 3), 1/2 bias (4) 1/3 duty (time multiplexing by 3), 1/3 bias (5) 1/4 duty (time multiplexing by 4), 1/3 bias * A frame frequency can be selected from among four in each display mode. * A maximum of 20 segment signal output pins (S12-S31) and four common signal bit port output (COM0COM3). * The segment signal output pins (S24-S27 and S28-S31) can be changed to the bit port output in 4-pin units. * Split-resistor can be incorporated to supply LCD drive power. (Mask option) * Various bias methods and LCD drive voltages can be applicable. * When display is off, current flow to the split resistor is cut. * Display data memory not used for display can be used for normal data memory. * It can also operate by using the subsystem clock. Data Sheet U11353EJ4V0DS00 33 LCD drive mode changer 34 4 Display data memory 1FFH 32 10 1FEH 32 10 Data Sheet U11353EJ4V0DS00 Figure 6-10. LCD Controller/Driver Block Diagram Internal bus 8 1F8H 32 10 1ECH 32 10 4 Display control register 4 Port 3 output latch 10 8 Port mode register group A 1F9H 32 10 Display mode register 10 32 10 32 10 32 10 32 10 32 10 Timing controller fLCD Multiplexer Selector PD753036, 753036(A) Segment driver Common driver LCD drive voltage control S31/BP7 S30/BP6 S24/BP0 S23 S12 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 P31/ P30/ SYNC LCDCL PD753036, 753036(A) 6.10 A/D Converter PD753036 incorporates an 8-bit resolution A/D converter with an analog input (AN0-AN7). It uses the successive approximation method. Figure 6-11. A/D Converter Block Diagram Internal bus 8 ADEN ADM6 ADM5 ADM4 SOC EOC 0 0 8 AN0 AN1 AN2 AN3 Multiplexer AN4 AN5 AN6/P82 AN7/P83 Sample hold circuit Control circuit + - Comparator SA register (8) 8 Tap decoder AVREF R/2 R R R R/2 Series resistor string AVSS ADEN Data Sheet U11353EJ4V0DS00 35 PD753036, 753036(A) 6.11 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-12. Bit Sequential Buffer Format Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0 BSB3 BSB2 BSB1 BSB0 L register L = FH L = CH L = BH L = 8H L = 7H L = 4H L = 3H DECS L L = 0H INCS L Remarks 1. 2. In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification. 36 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 7. INTERRUPT FUNCTION AND TEST FUNCTION The PD753036 has eight interrupt sources and two test sources. Of the test sources, INT2 has two types of edge-detected testable inputs. The interrupt control circuit of the PD753036 has the following functions: (1) Interrupt function q Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). Can set any interrupt start address. Nesting wherein the order of priority can be specified by the interrupt priority select register (IPS). Test function of interrupt request flag (IRQxxx). An interrupt generated can be checked by software. Release the standby mode. A release interrupt can be selected by the interrupt enable flag. q q q q (2) Test function q Test request flag (IRQxxx) generation can be checked by software. Release the standby mode. The test source to be released can be selected by the test enable q Data Sheet U11353EJ4V0DS00 37 38 2 1 4 IM2 IM1 IM0 INTBT INT4/P00 INT0/P10 INT1/P11 Note Selector Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus IME IPS Interruput enable flag (IExxx) IST1 IST0 Decoder IRQBT VRQn Both edge detector Edge detector Edge detector INTCS1 INTT0 INTT1 INTT2 INTW IRQ4 IRQ0 IRQ1 IRQCS1 IRQT0 IRQT1 IRQT2 IRQW IRQ2 Standby release signal Priority control circuit Vector table address generator Data Sheet U11353EJ4V0DS00 INT2/P12 Rising edge detector Selector KR0/P60 KR3/P63 Falling edge detector PD753036, 753036(A) IM2 Note Noise eliminator (Standby release is disable when noise eliminator is selected.) PD753036, 753036(A) 8. STANDBY FUNCTION In order to save power consumption while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD753036. Table 8-1. Operation Status in Standby Mode STOP Mode Set instruction System clock when set STOP instruction Settable only when the main system clock is used. The main system clock stops oscillation. HALT Mode HALT instruction Settable both by the main system clock and subsystem clock. Only the CPU halts (oscillation continues). Operation. (The IRQBT is set in the reference interval) Note 1. Operable Note 1 Operation status Clock generator Basic interval timer Operation stops Serial interface Operable only when an external SCK input is selected as the serial clock. Operable only when a signal input to the T10-T12 pins is specified as the count clock. Operable when fXT is selected as the count clock. Operable only when fXT is selected as the LCDCL. The INT1, 2, and 4 are operable. Only the INT0 is not operated. Note 2 The operation stops. Timer/event counter Operable Note 1 Watch timer Operable LCD driver controller Operable External interrupt CPU Release signal * Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag. * Test request signal sent from the test source enabled by the test enable flag * RESET signal Notes 1. 2. Cannot operate only when the main system clock stops. Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register(IM0). Data Sheet U11353EJ4V0DS00 39 PD753036, 753036(A) 9. RESET FUNCTION There are two reset inputs: external RESET signal and reset signal sent from the basic interval timer/watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 9-1 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal reset signal Reset signal sent from the basic interval timer/watchdog timer WDTM Internal bus By the RESET signal generation, each device is initialized as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operating mode or standby mode HALT mode Internal reset operation Operating mode Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms : at 6.0 MHz operation, 31.3 ms : at 4.19 MHz operation) 2 15/fX (5.46 ms : at 6.0 MHz operation, 7.81 ms : at 4.19 MHz operation) 40 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Table 9-1. Status of Each Device After Reset (1/2) RESET Signal Generation in the Standby Mode Sets the low-order 6 bits of program memory's address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. Held 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH RESET Signal Generation in Operation Sets the low-order 6 bits of program memory's address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. Undefined 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH Hardware Program counter (PC) PSW Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0, 1) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval timer/watchdog timer Timer/event counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer/event counter (T1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer/event counter (T2) Counter (T2) Modulo register (TMOD2) High level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB TGCE Watch timer Mode register (WM) 0 0, 0 0, 0, 0 0 0 0 0, 0 0, 0, 0 0 0 Data Sheet U11353EJ4V0DS00 41 PD753036, 753036(A) Table 9-1. Status of Each Device After Reset (2/2) RESET Signal Generation in the Standby Mode Held 0 0 Held 0 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 0 Off Cleared (0) 0 0 Held RESET Signal Generation in Operation Undefined 0 0 Undefined 0 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 0 Off Cleared (0) 0 0 Undefined Hardware Serial interface Shift register (SIO) Operating mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Clock generator, clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM) Sub-oscillator control register (SOS) LCD controller/ driver Interrupt function Display mode register (LCDM) Display control register (LCDC) Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt master enable flag (IME) INT0, 1, 2 mode registers (IM0, IM1, IM2) Interrupt priority selection register (IPS) Digital port Output buffer Output latch I/O mode registers (PMGA, PMGB, BMGC) Pull-up resistor setting register (POGA, POGB) Bit sequential buffer (BSB0-BSB3) 42 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 10. MASK OPTION The PD753036 has the following mask options. * P40-P43, P50-P53 mask options On-chip pull-up resistors can be connected. (1) On-chip pull-up resistors are specifiable bit-wise. (2) On-chip pull-up resistors are not specifiable. * VLC0-VLC2 pin, BIAS pin mask option On-chip dividing resistor for LCD drive can be connected. (1) Dividing resistor is not connected. (2) Four 10 k (TYP.) dividing resistors are connected at the same time. (3) Four 100 k (TYP.) dividing resistors are connected at the same time. * Standby function mask option Wait times can be selected by a RESET signal. (1) 217/fX (21.8ms : at fX = 6.0 MHz, 31.3ms : at fX = 4.19MHz) (2) 215/fX (5.46ms : at fX = 6.0 MHz, 7.81ms : at fX = 4.19MHz) * Subsystem clock mask option Use of the internal feedback resistor can be selected. (1) Internal feedback resistor can be used. (Switched ON/OFF via software) (2) Internal feedback resistor cannot be used. (Switched out in hardware) Data Sheet U11353EJ4V0DS00 43 PD753036, 753036(A) 11. INSTRUCTION SETS (1) Expression formats and specification methods of operands The operand is written in the operand column of each instruction in accordance with the specification method for the operand expression format of the instruction. For details, refer to RA75X Assembler Package User's Manual - Language (U12385E). If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are written as they are. For immediate data, appropriate numbers and labels are written. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be specified. However, there are restrictions in the labels that can be written for fmem and pmem. For details, refer to User's Manual. Representation format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IExxx RBn MBn Specification Method X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, BC, XA, BC, DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label Note FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-3FFFH immediate data or label 0000H-3FFFH immediate data or label (Mk II mode only) 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (where bit 0 = 0) or label PORT0-PORT8 IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW RB0-RB3 MB0, MB1, MB2, MB15 Note mem can be only used even address in 8-bit data processing. 44 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) (2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : A register, 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA' expanded register pair : BC' expanded register pair : DE' expanded register pair : HL' expanded register pair : Program counter : Stack pointer : Carry flag, bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 0-8) : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Separation between address and bit : The contents addressed by xx : Hexadecimal data Data Sheet U11353EJ4V0DS00 45 PD753036, 753036(A) (3) Explanation of symbols under addressing area column *1 MB = MBE*MBS (MBS = 0-2, 15) MB = 0 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0-2, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-3FFFH addr, addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 caddr = 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-3FFFH (PC13, 12 (PC13, 12 (PC13, 12 (PC13, 12 = = = = 00B) or 01B) or 10B) or 11B) *2 *3 Data memory addressing *4 *5 *6 *7 *8 Program memory addressing *9 *10 *11 Remarks 1. 2. 3. 4. MB indicates memory bank that can be accessed. In *2, MB = 0 independently of how MBE and MBS are set. In *4 and *5, MB = 15 independently of how MBE and MBS are set. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * When no skip is made: S = 0 * When the skipped instruction is a 1- or 2-byte instruction: S = 1 * When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 46 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Number of Machine Cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg1 XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String effect A String effect B Instruction Group Transfer Mnemonic Operand Number of Bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 Operation Addressing Area Skip Condition MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg1 XA, rp' reg1, A rp'1, XA String effect A XCH A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' Data Sheet U11353EJ4V0DS00 47 PD753036, 753036(A) Number of Machine Cycles 3 3 3 3 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 Instruction Group Table reference Mnemonic Operand Number of Bytes 1 1 1 1 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 Operation XA (PC13-8+DE)ROM XA (PC13-8+XA)ROM XA (B1,0+CDE)ROM XA (B1,0+CXA)ROM CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1, CY rp'1-XA-CY Addressing Area Skip Condition MOVT XA, @PCDE XA, @PCXA XA, @BCDENote XA, @BCXANote *6 *6 *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1 Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA *1 borrow borrow borrow SUBC A, @HL XA, rp' rp'1, XA *1 Note Only the low-order 2-bits are valid for the B register. 48 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Number of Machine Cycles 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA CY A0, A3 CY, An-1 An AA reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY CY=1 *1 *1 *1 *1 *3 reg=0 rp1=00H (HL)=0 (mem)=0 reg=FH rp'=FFH reg=n4 (HL) = n4 A = (HL) XA = (HL) A=reg XA=rp' *1 *1 *1 Instruction Group Operation Mnemonic Operand Number of Bytes 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 Operation Addressing Area Skip Condition AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA Accumulator manipulation RORC NOT A A reg rp1 @HL mem Increment and Decrement INCS DECS reg rp' Comparison SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY Data Sheet U11353EJ4V0DS00 49 PD753036, 753036(A) Number of Machine Cycles 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit)=1 Skip if (fmem.bit)=1 Skip if (pmem7-2+L3-2.bit(L1-0))=1 Skip if (H+mem3-0.bit)=1 Skip if (mem.bit)=0 Skip if (fmem.bit)=0 Skip if (pmem7-2+L3-2.bit(L1-0))=0 Skip if (H+mem3-0.bit)=0 Skip if (fmem.bit)=1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY v (fmem.bit) CY CY v (pmem7-2+L3-2.bit(L1-0)) CY CY v (H+mem3-0.bit) Instruction Group Memory bit manipulation Mnemonic Operand Number of Bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operation Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 Skip Condition SET1 mem.bit fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit (mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit 50 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Instruction Group Branch Number of Bytes - Number of Machine Cycles - Addressing Area *6 Mnemonic Operand Operation PC13-0 addr Select appropriate instruction from among BR !addr, BRCB !caddr, and BR $addr according to the assembler being used. BR !addr BRCB !caddr BR $addr PC13-0 addr1 Select appropriate instruction from the following according to the assembler being used. BR !addr BRA !addr1 BRCB !caddr BR $sddr1 PC13-0 addr PC13-0 addr PC13-0 addr1 PC13-0 PC13-8+DE PC13-0 PC13-8+XA PC13-0 B1,0+CDE PC13-0 B1,0+CXA PC13-0 addr1 PC13-0 PC13,12+caddr11-0 (SP-5)(SP-6)(SP-3)(SP-4) 0, 0, PC13-0 (SP-2) x, x, MBE, RBE PC13-0 addr1, SP SP-6 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 addr, SP SP-4 (SP-5)(SP-6)(SP-3)(SP-4) 0, 0, PC13-0 (SP-2) x, x, MBE, RBE PC13-0 addr, SP SP-6 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 000+faddr, SP SP-4 (SP-5)(SP-6)(SP-3)(SP-4) 0, 0, PC13-0 (SP-2) x, x, MBE, RBE PC13-0 000+faddr, SP SP-6 Skip Condition BRNote1 addr addr1 - - *11 !addr $addr $addr1 PCDE PCXA BCDENote 2 BCXANote 2 BRANote 1 BRCB !addr1 !caddr 3 1 1 2 2 2 2 3 2 3 2 2 3 3 3 3 3 2 *6 *7 *6 *6 *11 *8 Subroutine stack control CALLANote 1 !addr1 3 3 *11 CALLNote 1 !addr 3 3 *6 4 CALLFNote 1 !faddr 2 2 *9 3 Notes 1. 2. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Only the low-order 2 bits are valid for the B register. Data Sheet U11353EJ4V0DS00 51 PD753036, 753036(A) Number of Machine Cycles 3 Instruction Group Subroutine stack control Mnemonic Operand Number of Bytes 1 Operation MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+4 x, x, MBE, RBE (SP+4) 0, 0, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6 Addressing Area Skip Condition RETNote 1 RETSNote 1 1 3+S MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+4 then skip unconditionally x, x, MBE, RBE (SP+4) 0, 0, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6 then skip unconditionally Unconditional RETINote 1 1 3 MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 0, 0, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 PUSH rp BS 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1)(SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 IME(IPS.3) 1 IExxx 1 IME(IPS.3) 0 IExxx 0 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation (n = 0-8) (n = 4, 6) (n = 2-8) (n = 4, 6) POP rp BS Interrupt control EI IExxx DI IExxx 2 2 2 2 2 2 2 2 2 1 Input/output INNote 2 A, PORTn XA, PORTn OUTNote 2 PORTn, A PORTn, XA CPU control HALT STOP NOP Notes 1. 2. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. 52 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Number of Machine Cycles 2 2 3 RBS n MBS n Instruction Group Special Mnemonic Operand Number of Bytes 2 2 1 Operation Addressing Area Skip Condition SEL RBn MBn (n = 0-3) (n = 0-2, 15) *10 ------------ GETINotes 1, 2 taddr * When TBR instruction PC13-0 (taddr)5-0+(taddr+1) ---------------------------------- * When TCALL instruction (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 (taddr)5-0+(taddr+1) SP SP-4 ---------------------------------- ------------ * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed 1 3 * When TBR instruction PC13-0 (taddr)5-0+(taddr+1) PC14 0 Depending on the reference instruction - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - ------------- 4 * When TCALL instruction (SP-5)(SP-6)(SP-3)(SP-4) 0, 0, PC13-0 (SP-2) x, x, MBE, RBE PC13-0 (taddr)5-0+(taddr+1) SP SP-6 ------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - 3 * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed Depending on the reference instruction Notes 1. 2. The shaded box is applicable only to the Mk II mode. The other area is applicable only to Mk I mode. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. Data Sheet U11353EJ4V0DS00 53 PD753036, 753036(A) 12. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Other than ports 4, 5 Ports 4, 5 Pull-up resistor provided N-ch open drain Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +14 -0.3 to VDD + 0.3 Per pin Total of all pins Low-level output current IOL Per pin Total of all pins Ambient operating temperature Storage temperature TA Tstg -10 -30 30 200 -40 to +85Note -65 to +150 Unit V V V V V mA mA mA mA C C Output voltage High-level output current VO IOH Note To drive LCD in the normal mode, TA = -10 to +85C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Capacitance (TA = 25C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Pins other than tested pins: 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 54 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Oscillator Ceramic oscillator Recommended Circuit Parameter Oscillation frequency (fX) Note 1 Conditions MIN. 1.0 TYP. MAX. 6.0 Note 2 Unit MHz X1 X2 C1 VDD C2 Oscillation stabilization timeNote 3 After VDD has reached MIN. value of oscillation voltage range 1.0 4 ms Crystal resonator X1 X2 Oscillation frequency (fX) Note 1 6.0Note 2 MHz C1 VDD C2 Oscillation stabilization timeNote 3 VDD = 4.5 to 5.5 V 10 ms 30 6.0 Note 2 MHz External clock X1 input frequency (fX) Note 1 1.0 X1 X2 X1 input high-, low-level widths (tXH, tXL) 83.3 500 ns Notes 1. 2. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. If the oscillation frequency is 4.19 MHz < fX < 6.0 MHz at 1.8 V VDD < 2.7 V, do not select the processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle is less than 0.95 s, falling short of the rated value of 0.95 s. 3. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released. Caution When using the main system clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillator. Data Sheet U11353EJ4V0DS00 55 PD753036, 753036(A) Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Oscillator Crystal resonator Recommended Circuit Parameter Oscillation frequency (fXT)Note 1 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz XT1 XT2 R C3 VDD C4 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V 1.0 2 s 10 External clock XT1 XT2 XT1 input frequency (fXT)Note 1 32 100 kHz XT1 input high-, low-level widths (tXTH, tXTL) 5 15 s Notes 1. 2. The oscillation frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influences due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillator. The subsystem clock oscillator has a low amplification factor to reduce current consumption and is more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost care in wiring the subsystem clock oscillator. 56 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Recommended Oscillator Constants Ceramic resonator (TA = -20 to +80C) Oscillator Constant (pF) C1 TDK Corp. CCR1000K2 CCR4.19MC3 CCR5.0MC3 CCR6.0MC3 FCR4.19MC5 FCR5.0MC5 FCR6.0MC5 Murata Mfg. Co., Ltd. CSB1000JNote CSA2.00MG040 CST2.00MG040 CSA4.19MG CST4.19MGW CSA4.19MGU CST4.19MGWU CSA6.00MG CST6.00MGW CSA6.00MGU CST6.00MGWU Kyocera Corp. KBR-1000F/Y KBR-2.0MS KBR-4.19MKC KBR-4.19MSB PBRC 4.19A PBRC 4.19B KBR-6.0MKC KBR-6.0MSB PBRC 6.00A PBRC 6.00B - - Capacitor-contained model 6.0 - - 33 - - 33 1.9 5.5 Capacitor-contained model Capacitor-contained model - 1.0 2.0 4.19 6.0 4.19 1.0 4.19 5.0 6.0 4.19 5.0 6.0 1.0 2.0 100 100 - 30 - 30 - 30 - 30 - 100 68 - 33 100 100 - 30 - 30 - 30 - 30 - 100 68 - 33 1.8 2.0 1.9 5.5 5.5 5.5 Capacitor-contained model - 2.4 2.7 5.5 1.8 2.0 5.5 2.0 2.0 5.5 5.5 Rd = 2.2 k - Capacitor-contained model - Capacitor-contained model - Capacitor-contained model - Capacitor-contained model - Capacitor-contained model - 100 - C2 100 - Oscillation Voltage Range (VDD) MIN. (V) MAX. (V) 2.4 5.5 - Capacitor-contained model Manufacturer Part Number Frequency (MHz) Remark Data Sheet U11353EJ4V0DS00 57 PD753036, 753036(A) Note When using the CSB1000J (1.0 MHz) by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 2.2 k) is necessary (refer to the figure below). The resistor is not necessary when using the other recommended resonators. X1 CSB1000J C1 VDD X2 Rd C2 Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 58 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Low-level output current High-level input voltage VIH2 Ports 0, 1, 6-8, RESET VIH1 Symbol IOL Per pin Total of all pins Ports 2, 3 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 2.7 V VDD 5.5 V 0.7 VDD 1.8 V VDD < 2.7 V 0.9 VDD 0.8 VDD 1.8 V VDD < 2.7 V 0.9 VDD VIH3 Ports 4, 5 Pull-up resistor provided N-ch open drain 0.7 VDD 1.8 V VDD < 2.7 V 0.9 VDD 0.7 VDD 1.8 V VDD < 2.7 V 0.9 VDD VIH4 Low-level input voltage VIL2 Ports 0, 1, 6-8, RESET VIL1 X1, XT1 Ports 2-5 2.7 VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 VDD 5.5 V 1.8 V VDD < 2.7 V VIL3 High-level output voltage Low-level output voltage VOH VOL1 X1, XT1 SCK, SO, ports 2, 3, 6-8, BP0-BP7 IOH = -1.0 mA SCK, SO, ports 2-8, BP0-BP7 IOL = 15 mA VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, SB1 N-ch open drain Pull-up resistor 1 k High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 VIN = 13 V VIN = 0 V VIN = VDD Pins other than X1, XT1 X1, XT1 Ports 4, 5 (N-ch open drain) Pins other than ports 4, 5, X1, XT1 X1, XT1 Ports 4, 5 (N-ch open drain) When input instruction is not executed Port 4, 5 (N-ch open drain) When input instruction is executed High-level output leakage current ILOH2 Low-level output leakage current Internal pull-up resistor RL1 RL2 VIN = 0 V Ports 0-3, 6-8 (except pin P00) Ports 4, 5 (when mask option selected) 50 15 100 30 200 60 k k ILOL VOUT = 13 V VOUT = 0 V ILOH1 VOUT = VDD -30 VDD = 5.0 V VDD = 3.0 V -10 -3 -20 -6 3 3 20 20 -3 -20 -3 0.4 0.2 VDD V V VDD - 0.1 0 0 0 0 0 VDD - 0.5 0.2 2.0 Conditions MIN. TYP. MAX. 15 120 VDD VDD VDD VDD VDD VDD 13 13 VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 Unit mA mA V V V V V V V V V V V V V V V V A A A A A A A A A A A A SCK, SO/SB0, SB1, ports 2, 3, 6-8 Ports 4, 5 (Pull-up resistor provided) Ports 4, 5 (N-ch open drain) 20 -3 Data Sheet U11353EJ4V0DS00 59 PD753036, 753036(A) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter LCD drive voltage Symbol VLCD VAC0 = 0 Conditions TA = -40 to +85C TA = -10 to 85C VAC0 = 1 VAC currentNote 1 IVAC RLCD1 RLCD2 VODC IO = 1.0 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 VODS IO = 0.5 A 1.8 V VLCD VDD 0 0.2 V VAC0 = 1, VDD = 2.0 V 10% 50 5 0 MIN. 2.7 2.2 1.8 1 100 10 TYP. MAX. VDD VDD VDD 4 200 20 0.2 Unit V V V A k k V LCD divider resistorNote 2 LCD output voltage deviation Note 3 (common) LCD output voltage deviationNote 3 (segment) Supply currentNote 4 IDD1 6.00 MHzNote 5 crystal oscillation C1 = C2 = 22 pF 4.19 MHzNote 5 crystal oscillation C1 = C2 = 22 pF VDD = 5.0 V 10%Note 6 VDD = 3.0 V 10% HALT mode Note 7 2.5 0.6 0.9 0.5 1.7 0.33 0.7 0.3 12 5.5 12 9.2 9.2 8.5 3.0 8.5 4.6 4.6 0.05 0.02 7.5 1.8 2.7 1.0 4.5 1.0 2.0 0.9 35 16 24 27 18 25 12.0 17 13.8 9.2 10 5.0 3.0 mA mA mA mA mA mA mA mA IDD2 VDD = 5.0 V 10% VDD = 3.0 V 10% 10%Note 7 IDD1 VDD = 5.0 V 10%Note 6 VDD = 3.0 V HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 3.0 V, TA = 25C VDD = 3.0 V 10% VDD = 3.0 V, TA = 25C Lowvoltage mode Note 9 IDD2 IDD3 32.768 kHzNote 8 crystal oscillation Lowvoltage modeNote 9 Low current consumption mode Note 10 A A A A A A A A A A A A A IDD4 HALT mode VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 3.0 V, TA = 25C VDD = 3.0 V 10% VDD = 3.0 V, TA = 25C Low power consumption mode Note 10 IDD5 XT1 = 0V Note 11 VDD = 5.0 V 10% VDD = 3.0 V 10% TA = 25C STOP mode 0.02 Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. Clear VAC0 to 0 in the low-current mode and STOP mode. When VAC0 is set to 1, the current increases by about 1 A. Either RLCD1 or RLCD2 can be selected by mask option. Voltage deviation is the difference between the ideal values (VLCDn; n = 0, 1, 2) of the segment and common outputs and the output voltage. The current flowing through the internal pull-up resistor and the LCD divider resistor is not included. Including the case when the subsystem clock oscillates. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. When the device operates in low-speed mode with PCC set to 0000. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. When the sub-oscillator control register (SOS) is set to 0000. 10. When SOS is set to 0010. 11. When SOS is set to 00x1 and the sub-oscillator feedback resistor is not used (x: don't care). 60 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) AC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter CPU clock cycle timeNote 1 tCY Symbol Conditions Operates with main system clock Operates with subsystem clock VDD = 2.7 to 5.5 V MIN. 0.67 0.95 114 122 TYP. MAX. 64 64 125 Unit s s s MHz kHz (minimum instruction execution time = 1 machine cycle) TI0, TI1, TI2 input frequency fTI VDD = 2.7 to 5.5 V 0 0 1.0 275 TI0, TI1, TI2 input high-, low-level widths Interrupt input high-, low-level widths tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 1.8 s s s s s s s tINTH, tINTL INT0 IM02 = 0 IM02 = 1 Note 2 10 10 10 10 INT1, 2, 4 KR0-KR7 RESET low-level width tRSL Notes 1. The cycle time (minimum instruction execution time) of the CPU clock () is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock. Cycle time tCY [ s] tCY vs VDD (with main system clock) 64 60 6 5 Operation guaranteed range 4 3 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0). 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] Data Sheet U11353EJ4V0DS00 61 PD753036, 753036(A) Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK *** internal clock output): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level widths SI Note 1 tKL1, tKH1 setup time (vs. SCK ) tSIK1 tKSI1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKCY1/2-50 tKCY1/2-150 150 500 SI Note 1 hold time (vs. SCK ) SCK SO Note 1 output delay time VDD = 2.7 to 5.5 V Note 2 TYP. MAX. Unit ns ns ns ns ns ns ns ns 400 600 tKSO1 RL = 1 k VDD = 2.7 to 5.5 V 0 0 250 1000 ns ns CL = 100 pF Notes 1. 2. Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 2-wire and 3-wire serial I/O modes (SCK *** external clock input): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level widths tKL2, tKH2 SI Note 1 setup time (vs. SCK ) tSIK2 SI Note 1 hold time (vs. SCK ) SCK SONote 1 output delay time tKSI2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 400 1600 100 150 VDD = 2.7 to 5.5 V Note 2 TYP. MAX. Unit ns ns ns ns ns ns ns ns 400 600 tKSO2 RL = 1 k VDD = 2.7 to 5.5 V 0 0 300 1000 ns ns CL = 100 pF Notes 1. 2. Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 62 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) SBI mode (SCK *** internal clock output (master)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level widths tKL3, tKH3 SB0, 1 setup time (vs. SCK ) SB0, 1 hold time (vs. SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI3 tKSO3 RL = 1 k CL = 100 pF Note TYP. MAX. Unit ns ns ns ns ns ns ns VDD = 2.7 to 5.5 V tKCY3/2-50 tKCY3/2-150 tSIK3 VDD = 2.7 to 5.5 V 150 500 tKCY3/2 VDD = 2.7 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. SBI mode (SCK *** external clock input (slave)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level widths tKL4, tKH4 SB0, 1 setup time (vs. SCK ) SB0, 1 hold time (vs. SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI4 tKSO4 RL = 1 k CL = 100 pF Note TYP. MAX. Unit ns ns ns ns ns ns ns VDD = 2.7 to 5.5 V 400 1600 tSIK4 VDD = 2.7 to 5.5 V 100 150 tKCY4/2 VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines. Data Sheet U11353EJ4V0DS00 63 PD753036, 753036(A) A/D Converter Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V, 1.8 V AVREF VDD, AVSS = VSS) Parameter Resolution Absolute accuracyNote 1 VDD = AVREF VDD AVREF Conversion time Sampling time Analog input voltage Analog input impedance AVREF current tCONV tSAMP VIAN RAN IREF Note 2 Note 3 AVSS 1000 0.25 2.0 2.7 V VDD 1.8 V VDD < 2.7 V Symbol Conditions MIN. 8 TYP. 8 MAX. 8 1.5 3 3 168/fX 44/fX AVREF Unit bit LSB LSB LSB s s V M mA Notes 1. 2. 3. Absolute accuracy excluding quantization error (1/2LSB) Time until end of conversion (EOC = 1) after execution of conversion start instruction (40.1 s: fX = 4.19 MHz). Time until end of sampling after execution of conversion start instruction (10.5 s: fX = 4.19 MHz). 64 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) AC timing test points (except X1 and XT1 inputs) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Clock timing 1/fX tXL tXH VDD - 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD - 0.1 V XT1 input 0.1 V TI0, TI1, TI2 timing 1/fTI tTIL tTIH TI0, TI1, TI2 Data Sheet U11353EJ4V0DS00 65 PD753036, 753036(A) Serial transfer timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SI Input data tKSO1, 2 SO Output data 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0, 1 tKSO1, 2 66 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Serial transfer timing Bus release signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET input timing tRSL RESET Data Sheet U11353EJ4V0DS00 67 PD753036, 753036(A) Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = -40 to +85C) Parameter Data retention power supply current Release signal setup time Oscillation stabilization wait timeNote 1 Symbol VDDDR tSREL tWAIT Released by RESET Released by interrupt request Conditions MIN. 1.8 0 Note 2 Note 3 TYP. MAX. 5.5 Unit V s ms ms Notes 1. 2. 3. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. Either 217/fX or 215/fX can be selected by mask option. Set by the basic interval timer mode register (BTM). (Refer to the table below.) BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 fx = 4.19 MHz 0 1 1 1 220/fx (approx. 250 ms) 217/fx (approx. 31.3 ms) 215/fx (approx. 7.81 ms) 213/fx (approx. 1.95 ms) Wait Time fx = 6.0 MHz 220/fx (approx. 175 ms) 217/fx (approx. 21.8 ms) 215/fx (approx. 5.46 ms) 213/fx (approx. 1.37 ms) Data retention timing (when STOP mode released by RESET) Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD STOP instruction execution tSREL RESET tWAIT Data retention timing (standby release signal: when STOP mode released by interrupt signal) HALT mode STOP mode Data retention mode Operation mode VDD STOP instruction execution Standby release signal (interrupt request) tSREL tWAIT 68 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 13. CHARACTERISTIC CURVE (reference) IDD vs. VDD (main system clock: 6.0 MHz crystal resonator) (TA = 25 C) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 Main system clock HALT mode + 32 kHz oscillation 0.5 Supply current IDD (mA) 0.1 0.05 Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 1) 0.01 0.005 Crystal resonator Crystal resonator x1 x2 xT1 xT2 32.768 kHz 330 k 22 pF VDD 22 pF 6.0 MHz 22 pF 22 pF VDD 0.001 0 1 2 3 4 Supply voltage VDD (V) Data Sheet U11353EJ4V0DS00 5 6 7 8 69 PD753036, 753036(A) IDD vs. VDD (main system clock: 4.19 MHz crystal resonator) (TA = 25 C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation 0.5 Supply current IDD (mA) 0.1 0.05 Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 1) 0.01 0.005 x1 x2 xT1 xT2 32.768 kHz 330 k 22 pF VDD 22 pF Crystal resonator Crystal resonator 4.19 MHz 22 pF 22 pF VDD 0.001 0 1 2 3 4 Supply voltage VDD (V) 5 6 7 8 70 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) IOH vs. VDD - VOH (ports 2, 3, 6-8) (TA = 25 C) 15 VDD = 5 V 10 VDD = 5.5 V VDD = 4 V VDD = 3 V VDD = 2.2 V 5 VDD = 1.8 V 0 0 0.5 1.0 1.5 VDD - VOH [V] 2.0 2.5 3.0 Data Sheet U11353EJ4V0DS00 71 PD753036, 753036(A) IOL vs. VOL (ports 2, 3, 6-8) (TA = 25C) 40 VDD = 5 V VDD = 4 V VDD = 3 V 30 VDD = 5.5 V VDD = 2.2 V IOL [mA] 20 VDD = 1.8 V 10 0 0 0.5 1.0 VOL [V] 1.5 2.0 72 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 14. PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S CD Q R 80 1 21 20 F G H I M J P K S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. S80GC-65-3B9-6 Data Sheet U11353EJ4V0DS00 73 PD753036, 753036(A) 80 PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 61 41 40 detail of lead end S C D Q R 80 1 20 21 F G P H I M J K M N NOTE S L S ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.000.20 12.000.20 12.000.20 14.000.20 1.25 1.25 0.22 +0.05 -0.04 0.10 0.50 (T.P.) 1.000.20 0.500.20 0.145 +0.055 -0.045 0.10 1.050.07 0.100.05 55 1.27 MAX. P80GK-50-BE9-6 Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 74 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) 15. RECOMMENDED SOLDERING CONDITIONS Solder the PD753036 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 15-1. Soldering Conditions of Surface Mount Type (1) PD753036GC-xxx-3B9: 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) PD753036GC(A)-xxx-3B9: 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) Symbol of Recommended Condition IR35-00-3 VP15-00-3 WS60-00-1 Soldering Method Infrared reflow VPS Wave soldering Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (210C min.), Number of times: 3 max. Package peak temperature: 215C, Time: 40 seconds max. (200C min.), Number of times: 3 max. Soldering bath temperature: 260C max., Time: 10 seconds max., Number of times: 1 Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per side of device) - (2) PD753036GK-xxx-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5 mm pitch) Symbol of Recommended Condition IR35-107-2 Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (210C min.), Number of times: 2 max., Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (200C min.), Number of times: 2 max., Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per side of device) VPS VP15-107-2 Partial heating - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U11353EJ4V0DS00 75 PD753036, 753036(A) APPENDIX A. PD75336, 753036, 75P3036 FUNCTION LIST Parameter Program memory PD75336 Mask ROM 0000H-3F7FH (16256 x 8 bits) PD753036 Mask ROM 0000H-3FFFH (16384 x 8 bits) 000H-2FFH (768 x 4 bits) PD75P3036 One-time PROM 0000H-3FFFH (16384 x 8 bits) Data memory CPU Instruction execution time When main system clock is selected When subsystem clock is selected Pin 48 connection 50-53 55 57 Stack SBS register 75X High-End 0.95, 1.91, 15.3 s (at 4.19 MHz operation) 75XL CPU * 0.95, 1.91, 3.81, 15.3 s (at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (at 6.0 MHz operation) 122 s (at 32.768 kHz operation) P22/PCL P30-P33 P81 IC None P22/PCL/PTO2 P30/MD0-P33/MD3 P81/T12 VPP SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection n00H-nFFH (n = 0-2) When Mk I mode: 2-byte stack When Mk II mode: 3-byte stack Stack area Subroutine call instruction stack operation Instruction BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr 000H-0FFH 2-byte stack Unavailable When Mk I mode: unavailable When Mk II mode: available Available 3 machine cycles Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles 5 channels * Basic interval timer/watchdog timer: 1 channel * 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter, career generator, timer with gate) * Watch timer: 1 channel CALLF !faddr 2 machine cycles Timer 4 channels * Basic interval timer: 1 channel * 8-bit timer/event counter: 2 channels * Watch timer: 1 channel 76 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) PD75336 * , 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) Parameter Clock output (PCL) PD753036 PD75P3036 * , 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (Main system clock: at 6.0 MHz operation) * 2, 4, 32 kHz (Main system clock: during 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (Main system clock: at 6.0 MHz operation) BUZ output (BUZ) 2, 4, 32 kHz (Main system clock: at 4.19 MHz operation, or subsystem clock: at 32.762 kHz operation) Serial interface 3 modes are available * 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit * 2-wire serial I/O mode * SBI mode None Contained SOS register Feedback resistor cut flag (SOS.0) Sub-oscillator current cut flag (SOS.1) None Contained Register bank selection register (RBS) Standby release by INT0 Vectored interrupt Operating supply voltage Operating ambient temperature Package Yes No External: 3, internal: 4 VDD = 2.7 to 6.0 V TA = -40 to +85C * 80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5 mm pitch) * 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) Yes External: 3, internal: 5 VDD = 1.8 to 5.5 V Data Sheet U11353EJ4V0DS00 77 PD753036, 753036(A) APPENDIX B. DEVELOPMENT TOOLS The following development tools are provided for system development using the PD753036. In 75XL series, relocatable assemblers common to the entire series are used in combination with the device file for each product type. Language processor RA75X relocatable assembler Part number (product name) Host machine OS PC-9800 series MS-DOSTM Ver. 3.30 to Ver. 6.2 IBM PC/ATTM compatible machines Note Distribution media 3.5-inch 2HD S5A13RA75X Refer to "OS for IBM PC" 3.5-inch 2HC S7B13RA75X Device file Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 IBM PC/AT compatible machines Note Distribution media 3.5-inch 2HD Part number (product name) S5A13DF753036 Refer to "OS for IBM PC" 3.5-inch 2HC S7B13DF753036 Note Ver.5.00 and the upper versions of Ver.5.00 have the task swap function, but it cannot be used for this software. Remark The operation of the assembler and the device file is guaranteed only on the above host machines and OSs. 78 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) PROM write tools Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single chip microcontrollers containing PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256 Kbits to 4 Mbits. PROM programmer adapter for the PD75P3036GC. Connect the programmer adapter to PG-1500 for use. PA-75P316GK PROM programmer adapter for the PD75P3036GK. Connect the programmer adapter to PG-1500 for use. PROM programmer adapter for the PD75P3036KK-T. Connect the programmer adapter to PG-1500 for use. PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 Note IBM PC/AT compatible machines Refer to "OS for IBM PC" 3.5-inch 2HD Distribution media 3.5-inch 2HD Part number (product name) PA-75P328GC PA-75P3036KK-T Software PG-1500 controller S5A13PG1500 S7B13PG1500 Note Ver.5.00 and the upper versions of Ver.5.00 have the task swap function, but it cannot be used for this software. Remark The operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. Data Sheet U11353EJ4V0DS00 79 PD753036, 753036(A) Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the PD753036. The system configurations are described as follows. Hardware IE-75000-RNote 1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a PD753036 subseries, the emulation board IE-75300-R-EM and emulation probe EP-75336GC-R or EP-75336GK-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a IE-75001-R PD753036 sub-series, the emulation board IE-75300-R-EM and emulation probe EP-75336GC-R or EP-75336GK-R which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. IE-75300-R-EM Emulation board for evaluating the application systems that use the PD753036 subseries. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for the PD753036GC. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion socket EV-9200GC-80 which facilitates connection to a target system. Emulation probe for the PD753036GK. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion adapter TGK-080SDW which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232C and Centronics I/F and controls the above hardware on a host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 Note 3 IBM PC/AT compatible machines Refer to "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Distribution media 3.5-inch 2HD 5-inch 2HD Part number (product name) EP-75336GC-R EV-9200GC-80 EP-75336GK-R TGK-080SDWNote 2 Software IE control program S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X Notes 1. 2. Maintenance parts This is a product of Tokyo Eletech Corp. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics 2nd Department (TEL +81-6-6244-6672) 3. Ver.5.00 and the upper versions of Ver.5.00 have the task swap function, but it cannot be used for this software. Remarks 1. 2. The operation of the IE control program is guaranteed only on the above host machines and OSs. The PD753036 subseries consists of the PD753036 and 75P3036. 80 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) OS for IBM PC The following IBM PC OS's are supported. OS PC DOSTM Version Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote Ver. 5.0 to Ver. 6.22 5.0/VNote to 6.2/VNote J5.02/VNote MS-DOS IBM DOSTM Note Only English version is supported. Caution Ver.5.00 and the upper versions of Ver.5.0 have the task swap function, but it cannot be used for this software. Data Sheet U11353EJ4V0DS00 81 PD753036, 753036(A) APPENDIX C. RELATED DOCUMENTS Some of the following related documents are preliminary. Device Related Documents Document No. Japanese English U11353E (this document) U11575E U10201E U10453E Document Name PD753036 Data Sheet PD75P3036 Data Sheet PD753036 User's Manual 75XL Series Selection Guide U11353J U11575J U10201J U10453J Development Tool Related Documents Document No. Japanese IE-75000 R/IE-75001-R User's Manual Hardware IE-75300-R-EM User's Manual EP-75336GC/GK-R User's Manual PG-1500 User's Manual RA75X Assembler Package User's Manual Software PG-1500 Controller User's Manual Operation Language Structured Assembler Preprocessor PC-9800 Series (MS-DOS) Base IBM PC Series (PC DOS) Base EEU-846 U11354J U10644J U11940J U12622J U12385J U12598J EEU-704 EEU-5008 English EEU-1416 U11354E U10644E U11940E U12622E U12385E U12598E EEU-1291 U10540E Document Name Other Documents Document No. Japanese SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcontroller-Related Products by Third Parties X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E - English Document Name Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. 82 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) [MEMO] Data Sheet U11353EJ4V0DS00 83 PD753036, 753036(A) [MEMO] 84 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) [MEMO] Data Sheet U11353EJ4V0DS00 85 PD753036, 753036(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 86 Data Sheet U11353EJ4V0DS00 PD753036, 753036(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U11353EJ4V0DS00 87 PD753036, 753036(A) [MEMO] MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 |
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